Using ML to Model and Optimize Chip Geometry for Improved Lithography

Abstract

This thesis delves into the creation and application of a predictive model aimed at optimizing chip production on a wafer, while maintaining the on-resistance (Ron) of a MOSFET within acceptable limits. Through a systematic approach, various regression models were developed, including linear regression, Random Forest, XGBoost, and a Deep Neural Network (DNN), to predict chip quantities considering both wafer and chip geometry. Model performance was rigorously evaluated using mean absolute error, with a focus on comparing machine learning models to a geometry-based predictor. The DNN demonstrated superior accuracy and was integrated into an optimization algorithm that managed the balance between chip quantity and Ron value. This algorithm employed Differential Evolution to identify the optimal chip layout, expanding its scope by considering reticle-based scenarios. This work contributes valuable insights into semiconductor manufacturing and chip layout optimization, offering a method to enhance wafer productivity, efficiency, and cost-effectiveness.